S.-N. Chen
Shared-memory multiprocessors, discrete-event simulation, trace-driven memory simulation, multicache coherence
As the gap between processor and memory speeds continues to widen, methods for measuring memory system designs before they are implemented in hardware are becoming increasingly important. The performance of the bus protocol maintaining the coherence of the same data in all caches for the shared-memory multiprocessors can be measured in advance by many analytical methods, the inevitable use of a simplified assumption to analyze a computer system with increasing complexity restrictions the predetermined conditions of the analytical results. The study introduces the development, implementation and future work for a trace-driven memory simulator for shared-memory multiprocessors. The simulator can measure the performance for different multiprocessors architectures under real operating systems and applications as a reference for the decision on the design or modification of the system, with the aim of increasing production efficiency and save R&D expenses.
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