M.B.I. Reaz, M. Akter, F. Mohd-Yasin, F. Choong, M.I. Ibrahimy (Malyasia), and M. Kamada (Japan)
Encryption, DES, 3DES, FPGA, Synthesis, Hardware
Among all algorithms based on wavelet transform and zerotree quantization, Said and Pearlman’s set partitioning in hierarchical trees (SPIHT) algorithm is well known for its simplicity and efficiency. SPIHT’s high memory requirement is a major drawback for hardware implementation. In this study, a modification of SPIHT named Modified-SPIHT (MSPIHT) is presented. The MSPIHT coding algorithm is modified using one list to store the co-ordinates of wavelet coefficients instead of three lists of SPIHT, defines two terms number of error bits and absolute zerotree, and merges the sorting pass and the refinement pass together as one scan pass. Comparison of MSPIHT with SPIHT on different test images shows that for coding a 512×512, grey-level image, MSPIHT reduce execution time for coding at most 7 times and for decoding at most 11 times at low bit rate, saves at least 0.5625 MBytes of memory, and reduces minor peak signal-to noise ratio (PSNR) values. The algorithm is further downloaded into FPGA for hardware prototyping. Result shows that the hardware implementation speeded up the processing of images few thousands times faster than that of the results obtained from software (Matlab) simulations.
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