C.-Y. Lee and C.W. Chiou
Bit-parallel multiplier, modified Booth’s algorithm, finite field, AOP, ESP, subword parallel processing
This investigation presents an effective algorithm for computing multiplication over a class of GF(2m) based on both irreducible all one polynomials (AOPs) and equally spaced polynomials (ESPs). The proposed AOP-based multiplier uses the modified Booth’s algorithm to develop a new multiplexer-based bit-parallel multiplier that is simple and modular and such properties are important for VLSI hardware implementation. The multiplier requires m/4 (m + 1) MUX4×1 and (1.5m2 + 0.5m − 1) XOR gates. Its time delay is not greater than TM + (3 + log2 m/4 )TX, where TM and TX are the time delays of MUX4×1 and 2-input XOR gate, respectively. For a certain degree, an irreducible ESP with a high degree can be obtained from a corresponding irreducible AOP with a relatively very low degree. Using the subword parallel processing, the proposed AOP-based multiplier with low degree can also be adopted to realize ESP-based multipliers with high degrees.
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