P.S. Nair, S.K.K. Venkataswamy, S. Eratne, and E.B. John (USA)
Power, delay, leakage, full-adders
Full-adders are one of the most widely used components in arithmetic blocks. The energy consumption and delay of full-adders often play a vital role in the energy consumption and delay of digital computing systems. Due to this fact design decisions made at the full-adder level are likely to have system-wide repercussions. Continued scaling of CMOS technology has helped in making devices faster but at the cost of static power consumption. The recent commercial introduction of transistors based on high-k dielectric material is expected to bring down the problem of leakage power consumption to a great extent. In this paper, we analyze the leakage power consumption and delay in full-adder circuits based on high-k dielectric and traditional CMOS transistor models. The use of high-k/metal gate transistors resulted in more efficient operation in terms of the Power Delay Product (PDP). Compared to the traditional CMOS implementation, there was a PDP improvement of at least 61%, 65% and 66% at 45nm, 32nm and 22nm respectively when high-K/metal-gate transistors were employed.
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