A PC-CLUSTER-BASED FULLY DIGITAL REAL-TIME SIMULATION OF A FIELD-ORIENTED SPEED CONTROLLER FOR AN INDUCTION MOTOR

M. Ouhrouche, R. Beguenane, A.M. Trzynadlowski, J.S. Thongam, and M. Dub´-Dallaire

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  15. [15] J. Chiasson & L. Tolbert, A library of Simulink blocks forreal-time control of HEV traction drives, Proc. Future CarCongress, Arlington, VA, June 3–5, 2002, 30–41.Appendix A: List of SymbolsVsd, Vsq: stator voltages in the synchronously rotatingreference frameIsd, Isq: stator currents in the synchronously rotatingreference frameψrd, ψrq: rotor fluxes in the synchronously rotating ref-erence frameVsα, Vsβ: stator voltages in the stationary reference frameIsα, Isβ: stator currents in the stationary reference frameψrα, ψrβ: rotor fluxes in the stationary reference frameωr: rotor speed (rad/s)ωe: synchronous speed (rad/s)Rs, Ls: stator resistance and self inductanceRr, Lr: rotor resistance and self inductance.Lm: magnetic inductancep: number of pole pairsJ: total rotor inertia constant (kg · m2)F: damping coefficient (N · m · s)Tl: load torque (N · m)Appendix B: Real-Time Models Implementation inRT-Lab EnvironmentFigs. B1–B4 shows the details of the four blockdiagrams—respectively SS_CONTROLLERS, SS_INV_MOTOR, SM_BREAKOUT_BOX, and SC_USER_INTERFACE—used for IFOC implementation using RT-Lab simulator as shown in Fig. 6. These block diagramsare actually Simulink models grouped to form a subsystem.Figure B1. Details of the slave #1 (SS_CONTROLLERS)block diagram.226Figure B2. Details of the Slave #2 (SS_INV_MOTOR)block diagram.Figure B3. Details of the master (SM_BREAKOUT_BOX) block diagram.Figure B4. Details of the console (SC_USER_INTER-FACE) block diagram.Once the models are grouped into console (SC_), dataacquisition (SM_), and computation (SS_) subsystems,special blocks called OpComm blocks must be inserted intothe subsystems [6]. These are simple feed-through blocksthat intercept all incoming signals before sending them tocomputation blocks and provide information to RT-Labconcerning the type and size of these intercepted signals.This signal interception is mandatory because when asimulation model runs in the RT-Lab environment, allconnections between the main subsystems are replaced byhardware communication links.Memory blocks are added in each subsystem in order to take into account delays that might occur duringinformation exchange.

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