BIST POWER MINIMIZATION BY TRANSITION REDUCTION – A REVIEW

A. Sao∗ and A. Mohan∗

References

  1. [1] M. Abramovici, M.A. Breuer, & A.D. Friedman, Digital systemstesting and testable design. (New York: Computer SciencePress, 1990).
  2. [2] V.D. Agrawal, C.R. Kime, & K.K. Saluja, A tutorial on builtin self test, part 1: Principles, IEEE Design and Test ofcomputers, 10 (2), 1993, 73–82.
  3. [3] P. Girard, Low power testing of VLSI circuits: Problemsand solutions, IEEE International Symposium on Quality ofElectronic Design, 2000, 173–179.
  4. [4] Y. Zorian, A distributed BIST control scheme for complexVLSI devices, IEEE VLSI Test Symposium, 1999, 4–9.
  5. [5] N.H.E. Weste & K. Eshraghian, Principles of CMOS VLSIdesign: A system perspective, Second Edition (Reading, MA:Addison-Wesley, 1992).
  6. [6] S. Chakravarty & V.P. Dabholkar, Two techniques for minimiz-ing power dissipation in scan circuits during test application,Proc. 3rd Asian Test Symp., Nara, Japan, 1994, 324–329.
  7. [7] S. Wang & S.K. Gupta, ATPG for heat dissipation minimizationduring test application, IEEE Transactions on Computers,47 (2) 1998, 256–262.
  8. [8] D.S. Johnson, C. Aragon, L. McGeoch, & C. Schevon, Opti-mization by simulated annealing: An experimental evaluation;Part 1, graph partitioning, Operational Research, 37, 1989,865–892.
  9. [9] S. Wang & S.K. Gupta, ATPG for heat dissipation minimizationfor scan testing, Proc. IEEE-ACM Design Automation Conf.,Anaheim, CA, 1997, 614–619.304
  10. [10] S. Wang, Minimizing heat dissipation during test applica-tion, Ph.D. Dissertation, EE-Systems, University of SouthernCalifornia, Los Angeles, 1998.
  11. [11] P. Goel, An implicit enumeration algorithm to generate tests forcombinational logic circuits. IEEE Transactions on Computers,30 (3), 1981, 215–222.
  12. [12] F.D. Brglez & K. Kozminski, Combinational profiles of se-quential benchmark circuits, Proc. Int. Symp. on Circuits andSystems, 1989, 1929–1933.
  13. [13] Y. Bonhomme, P. Girard, L. Guiller, C. Landrualt, et al., Agated clock scheme for lower power scan testing of logic ICsor embedded core, IEEE Transactions on Computers, 2001,253–258.
  14. [14] B. Pouya & A. Crouch, Optimization trade-offs for vectorvolume and test power, IEEE Int. Test Conf., 2000, 863–872.
  15. [15] Y. Bonehomme, P. Girard, L. Guiller, C. Landrault, et al., Agated clock scheme for low power scan testing for logic ICs orembedded cores, Proc. 10th Asian Test Symp., 2001, 253–258.
  16. [16] J. Saxena, K.M. Butler, & L. Whetsel, An analysis of powerreduction techniques in scan testing, Proc. IEEE Int. TestConf., Baltimore, MD, 2001, 670–677.
  17. [17] S. Wang & S.K. Gupta, DS-LFSR: A BIST TPG for lowswitching activity, IEEE Transactions on Computer AidedDesign of Integrated Circuits and System, 21 (7), 2002, 842–851.
  18. [18] S. Wang & S.K. Gupta, DS-LFSR: A new BIST TPG for lowheat dissipation, Proc. IEEE Int. Test Conf., 1997, 848–857.
  19. [19] S.W. Golomb, Shift register sequences (Laguna Hills, CA:Aegean Park, 1982).
  20. [20] D. Ghosh, S. Bhunia, & K. Roy, A low complexity scanreordering algorithm for low power test-per-scan BIST,www.gigascale.org.
  21. [21] S. Dasgupta, C.H. Papadimitriou, & U.V. Vazirani, Introduc-tion to algorithms. Mcgraw-Hill Higher Education, Sep 2006(ISBN 13: 9780073523408, ISBN 10: 0073523402)
  22. [22] T.H. Cormen, C.E. Leiserson, & R.L. Rivest, Introduction toAlgorithms, (Cambridge, MA: The MIT Press, 2000).
  23. [23] I. Pomeranz, & S.M. Reddy, 3-Weight pseudo-random testgeneration based on a deterministic test set, Proc. Int. Conf.on VLSI Design, 1993, 1050–1058.
  24. [24] J. Waicukauski, E. Lindbloom, E. Eichelberger, & O. For-lenza, A method for generating weighted random pattern testpatterns, IEEE Transactions On Computers, 1989, 33 (2),149–161.
  25. [25] S. Wang, Low hardware overhead scan based 3-weight weightedrandom BIST, Proc. Int. Test Conf., 2001, 868–877.
  26. [26] S. Wang, Generation of low power dissipation and high faultcoverage patterns for scan-based BIST, Proc. Int. Test Conf.,2002, 834–842.
  27. [27] P. Girard, L. Guiller, C. Landrault, & S. Pravassoudovitch, Atest vector inhibiting technique for low energy BIST design,17th IEEE VLSI Test Symp., 1999, 407–412.
  28. [28] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, et al.,Low energy BIST design: Impact of the LFSR TPG parameterson the weighted switching activity, IEEE Int. Symp. on Circuitsand Systems, Orlando, FL, 1999.
  29. [29] S. Ghosh, E. MacDonald, S. Basu, & N.A. Touba, Lowpower weighted pseudo random BIST using special scan cells,GLSVLSI ’04, April 26–28, 2004, Boston, MA, USA.
  30. [30] M.F. AlShaibi & C.R. Kime, Fixed-biased pseudo-random builtin self-test for random pattern resistant circuits. Proc. Int.Test Conf., 1994, 929–938.
  31. [31] S. Wang & S.K. Gupta, LT-RTPG: A new test-per-scanBIST TPG for low heat Dissipation, IEEE Transactions OnComputer Aided Design of Integrated Circuits and Systems,25 (8), 2006, 1565–1574.
  32. [32] J. Lee & N.A. Touba, Low power BIST based on scan par-titioning, Proc. 2005 20th IEEE Symp. on Defect and FaultTolerance in VLSI Systems, August 2005, 33-41.

Important Links:

Go Back