FAST BENCHMARKING FOR PROCESSOR DESIGN

Afzal Hossain, Daniel J. Pease, and James S. Burns

References

  1. [1] T. Sherwood and J.J. Yi, Guest editors’ introduction: Com-puter architecture simulation and modeling, IEEE Micro,26 (4), 2006, 5–7.
  2. [2] Standard Performance Evaluation Corporation, http://www.spec.org/.
  3. [3] T.F. Wenisch, R.E. Wunderlich, M. Ferdman, A. Ailamaki,B. Falsafi, and J.C. Hoe, SimFlex: Statistical sampling ofcomputer system simulation, IEEE Micro, 26 (4), 2006, 19–31.
  4. [4] N.L. Binkert, R.G. Dreslinski, L.R. Hsu, K.T. Lim, A.G. Saidi,and S.K. Reinhardt, The M5 simulator: Modeling networkedsystems, IEEE Micro, 26 (4), 2006, 52–60.
  5. [5] M. Van Biesbrouck, B. Calder, and L. Eeckhout, Efficientsampling startup for SimPoint, IEEE Micro, 26 (4), 2006,32–42.
  6. [6] J.S. Burns, Parallel on-chip simultaneous multithreading,Ph.D. dissertation, University of Southern California, Los An-geles, CA, 2000.
  7. [7] A. Hossain, Trace Cache in simultaneous multithreading, Ph.D.dissertation, Syracuse University, New York, 2002.
  8. [8] M. Reshadi, P. Mishra, and N. Dutt, Hybrid-compiled sim-ulation: An efficient technique for instruction-set architec-ture simulation, ACM Transactions on Embedded ComputingSystem, 8 (3), 2009, 20:1–20:27.
  9. [9] J. Haskins and K. Skadron, Accelerated warmup for sampledmicroarchitecture simulation, ACM Transaction on Architec-ture and Code Optimization, 2 (1), 2005, 78–108.
  10. [10] D.B. Noonburg and J.P. Shen, Theoretical modeling of su-perscalar processor performance, Proc. 27th Int. Symp. onMicroarchitecture, San Jose, CA, 1994.
  11. [11] D. Burger and T.M. Austin, The SimpleScalar tool set, Ver-sion 2.0, University of Wisconsin–Madison Computer ScienceDepartment Technical Report #1342, June 1997.
  12. [12] G.S. Sohi, Instruction issue logic for high performance, inter-ruptible, multiple functional unit, pipelined computer, IEEETransaction on Computer, 39 (3), 1990, 349–359.
  13. [13] E. Rotenberg and S. Bennett, A Trace Cache microarchitectureand evaluation, IEEE Transactions on Computers, 48 (2), 1999,111–120.
  14. [14] A. Agarwal, M. Horowitz, and J. Hennessy, An analyticalcache model, ACM Transactions on Computer Systems, 7 (2),1989, 184–215.
  15. [15] S. Wallace and N. Bagherzadeh, Modeled and measured in-struction fetching performance for superscalar microprocessors,IEEE Transaction on Parallel and Distributed Systems, 9 (6),1998, 570–578.
  16. [16] A. Agarwal, Performance tradeoffs in multithreaded processors,IEEE Transactions on Parallel and Distributed Systems, 3 (5),1992, 525–539.
  17. [17] A. Hosain and D.J. Pease, Trace Cache performance, Inter-national Journal of Science & Technology, 15 (1–2), 2004,9–14.
  18. [18] A. Hossain, D. Pease, et al., Trace Cache miss rate, In-ternational Journal of Modeling & Simulation, 27 (3), 2007,203–210.
  19. [19] P.J. Denning, The working-set model for program behavior,Communications of the ACM, 11 (5), 1968, 323–333.
  20. [20] A. Hossain, D.J. Pease, J. Burns, and N. Parveen, A mathe-matical model of trace cache, 13th IEEE Conf. Application-Specific Systems, Architecture and Processors, San Jose, CA,2002.
  21. [21] A. Hossain, D. Pease, J. Burns, and N. Parveen, Trace Cacheperformance parameters, Proc. 2002 IEEE Int. Conf. on Com-puter Design: VLSI in Computers and Processors, Freiburg,Germany, 2002, 348–355.
  22. [22] A. Beg, Incorporating program characteristics into a processormodel, Proc. World Congress on Engineering and ComputerScience, San Francisco, CA, 2008.
  23. [23] D. Magenheimer and T. Christian, vBlades: Optimized par-avirtualization for the itanium family, 3rd Virtual MachineResearch & Tech Symp., San Jose, CA, 2004.

Important Links:

Go Back